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semiconductor 8-29 august 1997 hin230 thru hin241 +5v powered rs-232 transmitters/receivers features ? meets all rs-232e and v.28 speci?cations ? requires only single +5v power supply - (+5v and +12v - hin231 and hin239) ? hin233 and hin235 require no external capacitors ? onboard voltage doubler/inverter ? low power consumption ? low power shutdown function ? three-state ttl/cmos receiver outputs ? multiple drivers - 10v output swing for +5v lnput - 300 w power-off source impedance - output current limiting - ttl/cmos compatible - 30v/ m s maximum slew rate ? multiple receivers - 30v input voltage range -3k w to 7k w input impedance - 0.5v hysteresis to improve noise rejection description the hin230-hin241 family of rs-232 transmitters/receivers interface circuits meet all ela rs-232e and v.28 speci?cations, and are particularly suited for those applications where 12v is not available. they require a single +5v power supply (except hin231 and hin239) and features onboard charge pump volt- age converters which generate +10v and -10v supplies from the 5v supply. the hin233 and hin235 require no external capacitors and are ideally suited for applications where circuit board space is critical. the family of devices offer a wide variety of rs-232 transmitter/receiver combinations to accommodate various applications (see selection table). the drivers feature true ttl/cmos input compatibility, slew- rate-limited output, and 300 w power-off source impedance. the receivers can handle up to 30v, and have a 3k w to 7k w input impedance. the receivers also feature hysteresis to greatly improve noise rejection. applications ? any system requiring rs-232 communications port - computer - portable, mainframe, laptop - peripheral - printers and terminals - instrumentation - modems selection table part number power supply voltage number of rs-232 drivers number of rs-232 receivers external components low power shutdown/ttl three-state number of leads hin230 +5v 5 0 4 capacitors yes/no 20 hin231 +5v and +7.5v to 13.2v 2 2 2 capacitors no/no 16 hin232 +5v 2 2 4 capacitors no/no 16 hin233 +5v 2 2 none no/no 20 hin234 +5v 4 0 4 capacitors no/no 16 hin235 +5v 5 5 none yes/yes 24 hin236 +5v 4 3 4 capacitors yes/yes 24 hin237 +5v 5 3 4 capacitors no/no 24 hin238 +5v 4 4 4 capacitors no/no 24 hin239 +5v and +7.5v to 13.2v 3 5 2 capacitors no/yes 24 hin240 +5v 5 5 4 capacitors yes/yes 44 hin241 +5v 4 5 4 capacitors yes/yes 28 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1997 file number 3138.4
8-30 ordering information pin descriptions part number temp. range ( o c) package pkg. no. hin230cb 0 to 70 20 ld soic m20.3 hin230ib -40 to 85 20 ld soic m20.3 hin230by die hin231cb 0 to 70 16 ld soic m16.3 hin231ib -40 to 85 16 ld soic m16.3 hin231by die hin232cp 0 to 70 16 ld pdip e16.3 hin232cb 0 to 70 16 ld soic m16.3 hin232ip -40 to 85 16 ld pdip e16.3 HIN232IJ -40 to 85 16 ld cerdip f16.3 hin232ib -40 to 85 16 ld soic m16.3 hin232mj -55 to 125 16 ld cerdip f16.3 hin232by die hin233cp 0 to 70 20 ld pdip e20.3 hin234cb 0 to 70 16 ld soic m16.3 hin234ib -40 to 85 16 ld soic m16.3 hin234by die hin235cp 0 to 70 24 ld pdip e24.3 hin236cp 0 to 70 24 ld pdip e24.3 hin236cb 0 to 70 24 ld soic m24.3 hin236ip -40 to 85 24 ld pdip e24.3 hin236ib -40 to 85 24 ld soic m24.3 hin236by die hin237cp 0 to 70 24 ld pdip e24.3 hin237cb 0 to 70 24 ld soic m24.3 hin237ip -40 to 85 24 ld pdip e24.3 hin237ib -40 to 85 24 ld soic m24.3 hin237by die hin238cp 0 to 70 24 ld pdip e24.3 hin238cb 0 to 70 24 ld soic m24.3 hin238ip -40 to 85 24 ld pdip e24.3 hin238ib -40 to 85 24 ld soic m24.3 hin238by die hin239cb 0 to 70 24 ld soic m24.3 hin239ib -40 to 85 24 ld soic m24.3 hin239by die hin240cn 0 to 70 44 ld mqfp q44.10x10 hin240in -40 to 85 44 ld mqfp q44.10x10 hin240by die hin241cb 0 to 70 28 ld soic m28.3 hin241ib -40 to 85 28 ld soic m28.3 hin241ca 0 to 70 28 ld ssop m28.209 hin241ia -40 to 85 28 ld ssop m28.209 hin241by die part number temp. range ( o c) package pkg. no. pin function v cc power supply input 5v 10%. hin233 and hin235 5v 5%. v+ internally generated positive supply (+10v nominal), hin231 and hin239 requires +7.5v to +13.2v. v- internally generated negative supply (-10v nominal). gnd ground lead. connect to 0v. c1+ external capacitor (+ terminal) is connected to this lead. c1- external capacitor (- terminal) is connected to this lead. c2+ external capacitor (+ terminal) is connected to this lead. c2- external capacitor (- terminal) is connected to this lead. t in transmitter inputs. these leads accept ttl/cmos levels. an internal 400k w pull-up resistor to v cc is connected to each lead. t out transmitter outputs. these are rs-232 levels (nominally 10v). r in receiver inputs. these inputs accept rs-232 input levels. an internal 5k w pull-down resistor to gnd is connected to each input. r out receiver outputs. these are ttl/cmos levels. en enable input. this is an active low input which enables the receiver outputs. with en = 5v, the outputs are placed in a high impedance state. sd shutdown input. with sd = 5v, the charge pump is disabled, the receiver outputs are in a high impedance state and the transmitters are shut off. nc no connect. no connections are made to these leads. hin230 thru hin241
8-31 pinouts hin230 (soic) top view hin231 (soic) top view t3 out t1 out t2 out t2 in t1 in gnd c1+ v cc v+ c1- t4 out nc shutdown t5 out t5 in t4 in t3 in v- c2- c2+ 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c+ c- v- t2 out r2 in nc t2 in v+ gnd t1 out r1 in r1 out t1 in nc v cc r2 out v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t5 out t5 in t4 in t1 in t2 in t3 in t1 t2 t3 t4 t5 +5v 400k w +5v + 1 m f + 1 m f + 1 m f 5 4 2 3 14 1 15 20 16 19 8 10 9 13 v+ v- c1+ c1- c2+ c2- 17 shutdown 7 +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 1 m f 11 12 6 v cc +5v 16 v+ +7.5v to +13.2v 15 t1 out t2 out t1 in t2 in t1 t2 10 7 13 4 +5v 400k w +5v 400k w r1 out r1 in r1 12 11 5k w r2 out r2 in r2 5 6 5k w +12v to -12v voltage inverter 1 m f 3 v- c+ c- + 1 m f 1 2 + 14 hin230 thru hin241
8-32 hin232 (pdip, cerdip, soic) top view hin233 (pdip, soic) top view pinouts (continued) 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c1+ v+ c1- c2+ c2- r2 in t2 out v cc t1 out r1 in r1 out t1 in t2 in r2 out gnd v- 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 t2 in t1 in r1 out r1 in t1 out gnd (v+) c1+ v cc gnd (v-) c2- r2 out t2 out v- c2- r2 in c2+ v+ (c1-) c1- (c1+) v- (c2+) c2+ (c2-) note: pin numbers in parentheses are for soic package. v cc +5v 2 v+ 16 t1 out t2 out t1 in t2 in t1 t2 11 10 14 7 +5v 400k w +5v 400k w r1 out r1 in r1 13 12 5k w r2 out r2 in r2 8 9 5k w +10v to -10v voltage inverter 1 m f 6 v- c2+ c2- + 1 m f 4 5 +5v to 10v voltage inverter c1+ c1- + 1 m f 1 3 + 1 m f + + 1 m f 15 6 v cc t1 out t2 out r1 out r2 in t1 in t2 in r1 in t1 +5v + 0.1 m f 4 5 1 2 18 14 (8) 19 8 (13) 12 (10) v+ v- c1+ c1- c2+ c2- +5v 400k w gnd 9 gnd 17 r2 out no connect internal -10v supply internal +10v supply v- c2+ c2- 13 (14) 5k w 6 20 11 (12) 15 16 10 (11) 3 t2 +5v 400k w 5k w hin230 thru hin241
8-33 hin234 (soic) top view hin235 (pdip) top view pinouts (continued) 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 t1 out t2 out t2 in t1 in gnd v+ c1+ t3 out t4 in t3 in v- c2- c2+ c1- t4 out v cc 1 2 3 4 5 6 7 8 9 10 11 12 t4 out t3 out t1 out t2 out r2 in r2 out t2 in t1 in r1 out r1 in gnd v cc 16 17 18 19 20 21 22 23 24 15 14 13 r3 in t5 in sd en t5 out r4 out t3 in r5 out r5 in r3 out r4 in t4 in 6 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t4 in t1 in t2 in t3 in t1 t2 t3 t4 +5v + 1 m f + 1 m f + 1 m f 4 3 1 2 13 16 14 15 7 9 8 12 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 1 m f 10 11 5 12 v cc t1 out t1 in t1 +5v + 0.1 m f 6 2 3 18 1 19 24 10 400k w 13 14 r1 out r1 in r1 4 5 r2 out r2 in r2 23 22 r3 out r3 in r3 16 17 21 20 +5v t2 out t2 in +5v t3 out t3 in +5v t4 out t4 in +5v t5 out t5 in +5v 400k w 400k w 400k w 400k w t2 t3 t4 t5 gnd 9 r4 in r5 in r4 r5 11 15 7 8 r4 out r5 out en sd 5k w 5k w 5k w 5k w 5k w hin230 thru hin241
8-34 hin236 (pdip, soic) top view hin237 (pdip, soic) top view pinouts (continued) t3 out t1 out t2 out r1 in r1 out t2 in t1 in gnd v cc c1+ v+ c1- t4 out r2 out shutdown en t4 in r3 out v- c2- c2+ r2 in t3 in r3 in 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 t3 out t1 out t2 out r1 in r1 out t2 in t1 in gnd v cc c1+ v+ c1- t4 out r2 out t5 in t5 out t4 in r3 out v- c2- c2+ r2 in t3 in r3 in 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 9 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t4 in t1 in t2 in t3 in t1 t2 t3 t4 +5v + 1 m f + 1 m f + 1 m f 7 6 2 3 18 1 19 24 10 12 11 15 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 1 m f 13 14 r1 out r1 in r1 4 5 5k w r2 out r2 in r2 23 22 5k w r3 out r3 in r3 16 17 5k w en 20 21 shutdown 8 9 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t4 in t1 in t2 in t3 in t1 t2 t3 t4 +5v + 1 m f + 1 m f + 1 m f 7 6 2 3 18 1 19 24 10 12 11 15 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 1 m f 13 14 r1 out r1 in r1 4 5 5k w r2 out r2 in r2 23 22 5k w r3 out r3 in r3 16 17 5k w t5 out t5 in t5 21 20 +5v 400k w 8 hin230 thru hin241
8-35 hin238 (pdip, soic) top view hin239 (soic) top view pinouts (continued) t2 out t1 out r2 in r2 out t1 in r1 out r1 in gnd v cc c1+ v+ c1- t3 out r3 out t4 in t4 out t3 in r4 out v- c2- c2+ r3 in t2 in r4 in 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 r1 out r1 in gnd v cc v+ c1+ c1- v- r5 in r5 out r4 out r4 in t1 in r2 out r2 in t2 out t1 out r3 out nc (note) en t3 out t2 in r3 in t3 in 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 note: no connect 9 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t4 out t4 in t1 in t2 in t3 in t1 t2 t3 t4 +5v + 1 m f + 1 m f + 1 m f 5 18 2 1 19 24 21 20 10 12 11 15 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w +5v 400k w + 1 m f 13 14 r1 out r1 in r1 7 6 5k w r2 out r2 in r2 3 4 5k w r3 out r3 in r3 23 22 5k w r4 out r4 in r4 16 17 5k w 8 4 v cc +10v to -10v voltage inverter t1 out t2 out t3 out t1 in t2 in t3 in t1 t2 t3 +5v + 1 m f + 1 m f 24 23 19 20 16 13 6 7 5 8 v+ c1+ c1- +5v 400k w +5v 400k w +5v 400k w r1 out r1 in r1 2 5k w r2 out r2 in r2 21 22 5k w r3 out r3 in r3 18 17 5k w r4 out r4 in r4 12 11 5k w r5 out r5 in r5 9 10 5k w en 14 1 +7.5v to +13.2v v- 3 hin230 thru hin241
8-36 hin240 (mqfp) hin241 (soic, ssop) top view pinouts (continued) nc gnd nc r2 in nc t2 out t1 out t3 out t4 out r3 in r3 out t5 in nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 r4 out t4 in t3 in r5 out r5 in nc nc shut en t5 out r4 in r2 out t2 in t1 in r1 out r1 in v cc nc nc nc nc nc c1+ v+ c1- c2+ c2- v- nc nc nc down t3 out t1 out t2 out r2 in r2 out t2 in t1 in r1 out r1 in gnd v cc c1+ v+ c1- t4 out r3 out shutdown en r4 in t4 in r5 out r5 in v- c2- c2+ r3 in r4 out t3 in 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 19 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t1 in t2 in t3 in t1 t2 t3 +5v + 1 m f 1 m f + 1 m f 15 14 7 8 37 6 25 27 26 30 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w + 1 m f 28 29 r1 out r1 in r1 17 5k w r2 out r2 in r2 10 13 5k w r3 out r3 in r3 4 3 5k w r4 out r4 in r4 40 39 5k w r5 out r5 in r5 35 36 5k w en 42 16 t4 out t4 in t4 38 5 +5v 400k w t5 out t5 in t5 241 +5v 400k w shutdown 43 18 11 v cc +5v to 10v voltage doubler +10v to -10v voltage inverter t1 out t2 out t3 out t1 in t2 in t3 in t1 t2 t3 +5v + 1 m f + 1 m f + 1 m f 7 6 2 3 20 1 12 14 13 17 v+ v- c1+ c1- c2+ c2- +5v 400k w +5v 400k w +5v 400k w + 1 m f 15 16 r1 out r1 in r1 9 5k w r2 out r2 in r2 4 5 5k w r3 out r3 in r3 27 26 5k w r4 out r4 in r4 23 22 5k w r5 out r5 in r5 18 19 5k w en 24 8 t4 out t4 in t4 21 28 +5v 400k w shutdown 25 10
8-37 absolute maximum ratings thermal information v cc to ground . . . . . . . . . . . . . . . . . . . . . .(gnd -0.3v) < v cc < 6v v+ to ground . . . . . . . . . . . . . . . . . . . . . . . (v cc -0.3v) < v+ < 12v v- to ground . . . . . . . . . . . . . . . . . . . . . . . -12v < v- < (gnd +0.3v) input voltages t in . . . . . . . . . . . . . . . . . . . . . . . . . (v- -0.3v) < v in < (v+ +0.3v) r in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30v output voltages t out . . . . . . . . . . . . . . . . . . . . (v- -0.3v) < v txout < (v+ +0.3v) r out . . . . . . . . . . . . . . . . . . (gnd -0.3v) < v rxout < (v+ +0.3v) short circuit duration t out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous r out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous operating conditions temperature range hin-xxxcx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 o c to 70 o c hin-xxxix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c hin-xxxmx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) 16 ld pdip package . . . . . . . . . . . . . . 90 n/a 24 ld pdip package . . . . . . . . . . . . . . 75 n/a 16 ld soic (w) package . . . . . . . . . . 100 n/a 24 ld soic package . . . . . . . . . . . . . . 80 n/a 28 ld soic package . . . . . . . . . . . . . . 75 n/a 28 ld ssop package . . . . . . . . . . . . . 100 n/a 44 ld mqfp package . . . . . . . . . . . . . 80 n/a 16 ld cerdip package . . . . . . . . . . . 80 18 maximum junction temperature (hermetic package) . . . . . . . . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic, ssop, mqfp - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations test conditions: v cc = +5v 10%, (v cc = +5v 5% hin233 and hin235) t a = operating temperature range parameter test conditions min typ max units output voltage swing, t out transmitter outputs, 3k w to ground 5 9 10 v power supply current, i cc no load, t a = 25 o c, hin232-233 - 5 10 ma hin230, hin234-238, hin240-241 - 7 15 ma hin231, hin239 - 0.4 1 ma v+ power supply current, i cc hin231 - 1.8 5 ma hin239 - 5.0 15 ma shutdown supply current, i cc (sd) - 1 10 m a input logic low, t in , en, v ll t in , en, shutdown - - 0.8 v input logic high, v lh t in 2.0 - - v en, shutdown 2.4 - - v logic pullup current, i p t in = 0v - 15 200 m a rs-232 input voltage range, v in -30 - +30 v receiver input impedance, r in v in = 3v 3.0 5.0 7.0 k w receiver input low threshold, v ln (h-l) v cc = 5v, t a = 25 o c 0.8 1.2 - v receiver input high threshold, v in (l-h) v cc = 5v, t a = 25 o c - 1.7 2.4 v receiver input hysteresis, v hyst 0.2 0.5 1.0 v ttl/cmos receiver output voltage low, v ol i out = 1.6ma (hin231-hin233 i out = 3.2ma) - 0.1 0.4 v ttl/cmos receiver output voltage high, v oh i out = -1.0ma 3.5 4.6 - v output enable time, t en hin235, 236, 239, 240, 241 - 400 - ns output disable time, t dis hin235, 236, 239, 240, 241 - 250 - ns propagation delay, t pd rs-232 to ttl - 0.5 - m s instantaneous slew rate, sr c l = 10pf, r l = 3k w , t a = 25 o c (note 2) - - 30 v/ m s transition region slew rate, sr t r l = 3k w , c l = 2500pf measured from +3v to -3v or -3v to +3v -3-v/ m s output resistance, r out v cc = v+ = v- = 0v, v out = 2v 300 - - w rs-232 output short circuit current, i sc t out shorted to gnd - 10 - ma note: 2. guaranteed by design. hin230 thru hin241
8-38 detailed description the hin230 thru hin241 family of rs-232 transmitters/receiv- ers are powered by a single +5v power supply (except hin-231 and hin239), feature low power consumption, and meet all ela rs-232c and v.28 speci?cations. the circuit is divided into three sections: the charge pump, transmitter, and receiver. charge pump an equivalent circuit of the charge pump is illustrated in figure 1. the charge pump contains two sections: the voltage dou- bler and the voltage inverter. each section is driven by a two phase, internally generated clock to generate +10v and -10v. the nominal clock frequency is 16khz. during phase one of the clock, capacitor c1 is charged to v cc . during phase two, the voltage on c1 is added to v cc , producing a signal across c3 equal to twice v cc . during phase one, c2 is also charged to 2v cc , and then during phase two, it is inverted with respect to ground to produce a signal across c4 equal to -2v cc . the charge pump accepts input voltages up to 5.5v. the output impedance of the voltage doubler section (v+) is approxi- mately 200 w , and the output impedance of the voltage inverter section (v-) is approximately 450 w . a typical applica- tion uses 1 m f capacitors for c1-c4, however, the value is not critical. increasing the values of c1 and c2 will lower the out- put impedance of the voltage doubler and inverter, increasing the values of the reservoir capacitors, c3 and c4, lowers the ripple on the v+ and v- supplies. during shutdown mode (hin230, 236, 240 and 241), shut- down control line set to logic 1, the charge pump is turned off, v+ is pulled down to v cc , v- is pulled up to gnd, and the supply current is reduced to less than 10 m a. the transmitter outputs are disabled and the receiver outputs are placed in the high impedance state. transmitters the transmitters are ttl/cmos compatible inverters which translate the inputs to rs-232 outputs. the input logic thresh- old is about 26% of v cc , or 1.3v for v cc = 5v. a logic 1 at the input results in a voltage of between -5v and v- at the output, and a logic 0 results in a voltage between +5v and (v+ -0.6v). each transmitter input has an internal 400k w pullup resistor so any unused input can be left unconnected and its output remains in its low state. the output voltage swing meets the rs-232c speci?cations of 5v minimum with the worst case conditions of: all transmitters driving 3k w minimum load impedance, v cc = 4.5v, and maximum allowable operating temperature. the transmitters have an internally limited output slew rate which is less than 30v/ m s. the outputs are short cir- cuit protected and can be shorted to ground inde?nitely. the powered down output impedance is a minimum of 300 w with 2v applied to the outputs and v cc = 0v. receivers the receiver inputs accept up to 30v while presenting the required 3k w to 7k w input impedance even it the power is off (v cc = 0v). the receivers have a typical input threshold of 1.3v which is within the 3v limits, known as the transition region, of the rs-232 speci?cations. the receiver output is 0v to v cc . the output will be low whenever the input is greater than 2.4v and high whenever the input is ?oating or driven between +0.8v and -30v. the receivers feature 0.5v hysteresis to improve noise rejection. the receiver enable line en, when set to logic 1, (hin236, 239, 240, and 241) disables the receiver outputs, placing them in the high impedance mode. the receiver outputs are also placed in the high impedance state when in shutdown mode. + - c1 + - c3 + - c2 + - c4 s1 s2 s5 s6 s3 s4 s7 s8 v cc gnd rc oscillator v cc gnd v+ = 2v cc gnd v- = -(v+) c1 + c1 - c2 - c2 + voltage inverter voltage doubler figure 1. charge pump t out v- < v tout < v+ 300 w 400k w t xin gnd < t xin < v cc v- v+ v cc figure 2. transmitter r out gnd < v rout < v cc 5k w r xin -30v < r xin < +30v gnd v cc figure 3. receiver t in v ol v ol t plh t phl average propagation delay = t phl + t plh 2 or r in t out or r out figure 4. propagation delay definition hin230 thru hin241
8-39 typical performance curves figure 5. v- supply voltage vs v cc , varying capacitors figure 6. v+, v- output voltage vs load 12 10 8 6 4 2 0 3.5 4.0 4.5 6.0 v cc v- supply voltage 5.0 5.5 3.0 0.10 m f 0.47 m f 1 m f 35 |i load | (ma) v+ (v cc = 4v) v+ (v cc = 5v) v- (v cc = 5v) v- (v cc = 4v) t a = 25 o c transmitter outputs open circuit 30 25 20 15 10 5 0 supply voltage (|v|) 0 12 10 8 6 4 2 test circuits (hin232) figure 7. general test circuit figure 8. po wer-off source resistance configuration 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c1+ v+ c1- c2+ c2- v- r2 in 12 out v cc t1 out r1 in r1 out t1 in t2 in r2 out gnd +4.5v to +5.5v input 3k w t1 output rs-232 30v input ttl/cmos output ttl/cmos input ttl/cmos input ttl/cmos output + - 1 m f c3 + - 1 m f c1 + - 1 m f c2 + - 1 m f c4 3k w output rs-232 30v input t2 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 c1+ v+ c1- c2+ c2- v- r2 in 12 out v cc t1 out r1 in r1 out t1 in t2 in r2 out gnd t2 out t1 out v in = 2v a r out = v in /1 hin230 thru hin241
8-40 applications the hinxxx may be used for all rs-232 data terminal and communication links. it is particularly useful in applications where 12v power supplies are not available for conven- tional rs-232 interface circuits. the applications presented represent typical interface con?gurations. a simple duplex rs-232 port with cts/rts handshaking is illustrated in figure 9. fixed output signals such as dtr (data terminal ready) and dsrs (data signaling rate select) is generated by driving them through a 5k w resistor connected to v+. in applications requiring four rs-232 inputs and outputs (figure 10), note that each circuit requires two charge pump capacitors (c1 and c2) but can share common reservoir capacitors (c3 and c4). the bene?t of sharing common res- ervoir capacitors is the elimination of two capacitors and the reduction of the charge pump source impedance which effectively increases the output swing of the transmitters. - + - + - + ctr (20) data terminal ready dsrs (24) data signaling rate rs-232 inputs and outputs td (2) transmit data rts (4) request to send rd (3) receive data cts (5) clear to send signal ground (7) 15 8 13 7 14 16 - + 6 r2 r1 t2 t1 9 12 10 11 4 5 3 1 hin232 c1 1 m f c2 1 m f td rts rd cts select +5v inputs outputs ttl/cmos figure 9. simple duplex rs-232 port with cts/rts handshaking - + rs-232 inputs and outputs dtr (20) data terminal ready dsrs (24) data signaling rate select dcd (8) data carrier detect r1 (22) ring indicator signal ground (7) 15 8 13 7 14 2 - + 4 r2 r1 t2 t1 9 12 10 11 3 1 hin232 c1 1 m f dtr dsrs dcd r1 +5v inputs outputs ttl/cmos - + - + td (2) transmit data rts (4) request to send rd (3) receive data cts (5) clear to send 8 13 7 14 15 r2 r1 t2 t1 9 12 10 11 4 5 3 1 hin232 c1 1 m f c2 1 m f td rts rd cts inputs outputs ttl/cmos - + 5 c2 1 m f 16 c3 2 m f 6 2 6 v- v+ - + c4 2 m f 16 figure 10. combining two hin232s for 4 pairs of rs-232 inputs and outputs hin230 thru hin241
8-41 die characteristics die dimensions: 160 mils x 140 mils metallization: type: al thickness: 10k ? 1k ? substrate potential v+ passivation: type: nitride over silox nitride thickness: 8k ? silox thickness: 7k ? transistor count: 238 process: cmos metal gate metallization mask layout hin240 t3 out t1 out t2 out r2 in r2 out t2 in t1 in r1 out r1 in gnd v cc c1+ v+ c1- t4 out r3 out en r4 in t4 in r5 out v- c2- c2+ r3 in r4 out t3 in r5 in shutdown t5 out t5 in hin230 thru hin241

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